1. Field of the Invention
The present invention relates to a display panel driver, and more particularly, to a technique for reducing the influence of an electrostatic protection resistor, which is connected to a pad, in an output circuit of a display panel driver.
2. Description of the Related Art
When a display panel driver, such as an LCD (liquid crystal display) driver, is implemented as an integrated circuit, an electrostatic protection resistor is typically inserted in series between an output stage of an output circuit and a pad. This is because the elimination of the series-connected electrostatic protection resistor may require a special measure, including an undesired increase in the transistor size of the output stage and use of an electrostatic protection element as an output transistor. Such special measure, however, may cause various problems, including undesired increases in the parasitic capacitance and the chip size, difficulty in achieving of desired characteristics.
When an electrostatic protection resistor is inserted in series between the output stage of the output circuit and the pad, the resistance value of the electrostatic protection resistor is set within a range that meets a certain standard determined to protect internal transistors from static electricity. The electrostatic protection resistor is typically set to a resistance value within the range of several tens to several hundreds ohms (Ω). If the resistance value is smaller than the range, the electrostatic protection standard determined in the MIL standard (Military Standard) or EIAJ (Electronic Industries Association of Japan) standard cannot be met.
The connection of the electrostatic protection resistor to the output circuit of the display panel driver, however, undesirably deteriorates the output characteristics of the output circuit. In the following, we discuss the deterioration of the output characteristics caused by the connection of the electrostatic protection resistor to the output circuit.
FIG. 1 is a circuit diagram illustrating an example of an output circuit of an LCD driver using analog amplifier circuits. FIG. 1 illustrates only a part corresponding to two output pads of the output circuit. The output circuit of the LCD driver in FIG. 1 is provided with a negative-side amplifier 101, a positive-side amplifier 102, an even output pad 103, an odd output pad 104, a common line 105, electrostatic protection resistors RESD1 and RESD2, and switches S1 to S7. The negative- and positive-side amplifiers 101 and 102 are both voltage-follower connected, of which non-inverting input terminals are connected to positive- and negative-side D/A converters (Digital to Analog converters).
The switch S1 is connected between an even output node NOUT1 and an output of the negative-side amplifier 101, and the switch S2 is connected between an odd output node NOUT2 and an output of the positive-side amplifier 102. The switch S3 is connected between the odd output node NOUT2 and the output of the negative-side amplifier 101, and the switch S4 is connected between the even output node NOUT1 and the output of the positive-side amplifier 102. The switches S1 to S4 are operated in conjunction with one another. The switch S5 is connected between the even output node NOUT1 and the odd output node NOUT2; the switch S6 is connected between the odd output node NOUT2 and the common line 105; and the switch S7 is connected between the even node NOUT1 and the common line 105. The switches S5 to S7 are operated in conjunction with one another.
On the other hand, the electrostatic protection resistor RESD1 is connected between the even output node NOUT1 and the even output pad 103, and the electrostatic protection resistor RESD2 is connected between the odd output node NOUT2 and the odd output pad 104. It should be noted that, although it is general in practice to use electrostatic protection diodes and the like in addition to the electrostatic protection resistors RESD1 and RESD2 for electrostatic protection, the electrostatic protection diodes in the circuit diagram are not shown and no description thereof is given; the electrostatic protection diodes and the like are not directly related to the present invention.
Although effectively avoiding electrostatic breakdown, the electrostatic protection resistors RESD1 and RESD2 undesirably deteriorate the waveforms of the output signals. Illustrated in FIG. 2 is an output waveform for a case where a rectangular wave is inputted to an input terminal, which is plotted for various resistance values of the electrostatic protection resistor. As is understood from FIG. 2, the output waveform is undesirably rounded as the resistance value of the electrostatic protection resistor is increased. Although ideal characteristics are obtained when the resistance value of the electrostatic protection resistor is zero, the electrostatic resistor having a non-zero resistance value should be inserted in practice, and therefore the characteristics are limited depending on the resistance value.
On the other hand, a circuit configuration for reducing the influence of the electrostatic protection resistor on an output circuit of a digital circuit is disclosed in, for example, Japanese Patent Application Publication JP 2001-358300A. In the following, a description is given of the output circuit disclosed in this patent application with reference to FIG. 3. The output circuit shown in FIG. 3 is provided with n PMOS transistors MP1 to MPn, n NMOS transistors MN1 to MNn, PMOS electrostatic protection resistors RP1 to RPn, NMOS electrostatic protection resistors RN1 to RNn, an internal circuit 106, an output terminal pad 107, and an inverter 108. The sources of the PMOS transistors MP1 to MPn are commonly connected to a power supply line of the positive power supply voltage (VDD), and the sources of the NMOS transistors MN1 to MNn are commonly connected to a power supply line of the negative power supply voltage (VSS). The inverter 108 has an input connected to the output terminal pad 107 and an output connected to the internal circuit 106. The gates of the PMOS transistors MP1 to MPn and the NMOS transistors MN1 to MNn are commonly connected to the output of the internal circuit 106. Also, the PMOS electrostatic protection resistors RP1 to RPn are connected between the drains of the PMOS transistors MP1 to MPn and the output terminal pad 107, and the NMOS electrostatic protection resistors RN1 to RNn are connected between the drains of the NMOS transistors MN1 to MNn and the output terminal pad 107.
Referring to FIG. 3, the PMOS and NMOS electrostatic protection resistors RP1 to RPn and RN1 to RNn are used to prevent the MOS transistors from being broken by an electrostatic surge, and the resistance values of the resistors are typically around several tens to several hundreds ohms, depending on the device manufacture process. Actual resistance values of the electrostatic protection resistors RP1 to RPn and RN1 to RNn, which vary depending on the actual accuracy of each device process, should be adjusted to resistance values which meet the standard. As described above, the voltage drop across the electrostatic protection resistor may cause deterioration in the characteristics of the output circuit; however, as illustrated in FIG. 3, the use of parallel-connected MOS transistors allows distributing flowing currents to the n electrostatic protection resistors. That is, the current through each electrostatic protection resistor is reduced down to 1/n of the original current. This also reduces the voltage drop caused by the current through each electrostatic protection resistor to 1/n, consequently avoiding the deterioration in the characteristics of the output circuit.
As described above, it is known that the output characteristics are improved as the resistance value of the electrostatic protection resistor is decreased. Accordingly, one potential approach based on the same idea as that underlying the circuit illustrated in FIG. 3 may be the use of multiple signal outputs to decrease the effective resistance value of each electrostatic protection resistor. However, the circuit in FIG. 3 is merely one example of the application to the output circuit in the digital circuit, and therefore the conventional technique cannot be directly applied to the example where the switch circuit is inserted into the output as in the output circuit of the display panel driver as illustrated in FIG. 1. This is because a transistor switch circuit and a CMOS logic circuit are completely different in nature. A switch may consist of a single N-channel MOS transistor, a single P-channel MOS transistor, or a transfer gate circuit, which is provided with paired NMOS and PMOS transistors. Since the output circuit of the display panel driver is different in nature from the circuit shown in FIG. 3, the optimum approach may be different from that for the conventional circuit shown in FIG. 3. That is, one issue is that the conventional approach cannot be simply applied to the output circuit of the display panel driver.